Principal Firmware/VHDL Engineer

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Listing Info

Raytheon Missile Systems (RMS) is the world leader in design, development and production of missile systems. RMS produces systems for diverse defense applications including air-to-air, strike, surface Navy air defense, land combat, guided projectiles, exo-atmospheric kill vehicles, and directed energy weapons. Headquartered in Tucson, AZ, RMS employs over 11,000 people and generated over $5.5 billion in 2011 revenues.

The Electronics Center performs electronics development and support for missile systems, from concept to manufacturing. These activities include concept definition, subsystems engineering, digital and analog circuit design, FPGA and ASIC design, power supply design, first article test and production support.

The vision of the Electronics Center is to provide electronic design solutions which exceed customer expectations, on time and on budget. To accomplish this we maintain a world class engineering organization and we place great emphasis upon providing exciting work opportunities and career development for our employees.

Bring your talent and skills to the Electronics Center's Configurable Digital Logic Department.

Job Description

Personnel in the Configurable Digital Logic (CDL) Department develop and verify FPGA designs for all major vendors and device families including: Xilinx, Altera, Lattice, and Microsemi. The Department also designs digital ASICs and performs obsolescence mitigation activities, including redesign, for digital ASICs. Designs are implemented using VHDL for the following applications: gigabit serial interfaces, Radio Frequency (RF) and Electro-Optical (EO) DSP, controls, data links, embedded processing and processor interfaces. Designers work with circuit card designers and systems engineers to develop requirements, architect new parts, partition and perform code development, simulation, place and route. Designs are verified against requirements using both directed test and constrained random methodologies. Design support is expected from requirements definition through integration and test. Design documentation and configuration management are required.

Responsibilities

The CDL Department is deploying a Unified Verification Methodology (UVM) based verification capability and is seeking a senior verification engineer to lead all aspects of development, deployment and execution of the Department's verification strategy. Responsibilities include, but are not limited to:

  • Participating in the functional verification of ASICs/FPGAs as-needed
  • Leading and mentoring teams of verification engineers
  • Creating the verification plan with the Program and RTL designers input and review.
  • Developing the architecture and design of the environment as well as participating and/or leading a team of engineers to implement the test benches.
  • Creating the necessary run and/or post-processing scripts as well as the overall methodology for the given project in terms of the logistics related to using the verification environment
  • Implementation of the verification environment, including:
  • Creation of Constrained Random Agents
  • Creation of Monitors and Scoreboards
  • Incorporation of available models that may exist as C/C++, Verilog or VHDL, etc., and/or creation of those models
  • Creation of functional coverage through use of assertions, etc.
  • Use of functional and code coverage as a quantitative measure to analyze and help determine what is considered 100% coverage for the given design as determined by the verification plan.
  • Writing directed and constrained random tests


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