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Cache and Coherent Interconnect Verification Engineer - Raleigh, NC (RTP)

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Listing Info

Requisition # G1906657
Job Title Cache and Coherent Interconnect Verification Engineer - Raleigh, NC (RTP)
Post Date 04/29/2013
Company

  • Division Qualcomm Technologies, Inc.

    • Engineering - Apps Processors

    Location North Carolina - Raleigh

    Job Function Qualcomm CDMA Technologies, a.k.a. QCT - http://www.qualcomm.com/qct/, is the world leader in wireless ICs powering the majority of 3G & 4G devices, is the largest fabless semiconductor in the world, and is consistently ranked near the top of Fortune's list of "100 Best Companies to Work For." QCT's IP Development Team is looking for an experienced Hardware Verification Engineer to verify a high performance cache controller, hardware coherent interconnect, and memory subsystem for next generation products. The verification engineer will be part of a design and verification team with responsibility for test planning, testcase execution, as well as functional and code coverage closure. The successful applicant will work to support and develop verification infra-structure of Bus interconnect IP and coherent cache controller core deliverables.
    Responsibilities The role requires a detailed working knowledge of the AMBA AHB and AXI bus protocols and experience with a coverage based verification language preferably SVTB or Vera. Typical tasks include the development of new infra-structure and testcases, interfacing with customer teams and debugging their issues, and releasing new versions of the IP core. The candidate must be familiar with verification/test planning, coverage closure, release methodology, and revision control systems. Additionally, the candidate must be a self starter, possess excellent analytical and problem solving/debugging skills, and have excellent verbal and written communication skills.

    Skills/Experience Required

  • 2-5 Years design verification experience (System Verilog, Verilog) - Familiarity with industry standard verification methodology like RVM, VMM, OVM, Perl, Make, Objected Oriented Programming Preferred: - 1-2 Years design experience (synthesis, gate-level/SDF simulation) - Development of protocol IP - Knowledge of SVAs (standard OVL library and custom)
    Education Requirements *LI-SRC" id="hdnEducationalRequirements" />Required: Bachelor's, Computer Engineering and/or Electrical Engineering Preferred: Master's, Computer Engineering and/or Electrical Engineering

    • LI-SRC

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